Computer Organization & Architecture — GeeksforGeeks · tpointtech tutorial
CSS Computer Science (Optional) — Paper-II, Section-A, Topic I.
Organised by conceptual category (Foundations → Processor/CPU → Instructions & Control → Data & Arithmetic → Parallel Architecture → Memory System → I/O & Interconnection), rather than flat textbook chapter order — so topics that get compared against each other in the exam (e.g. SRAM vs DRAM, cache vs virtual memory, multiprocessor vs multicore, hardwired vs micro-programmed control) now sit together instead of being scattered across a flat list. Each subpage still follows the same internal structure: Definition → Classification → Diagram → Solved Numericals → CSS Exam Angle → Repeated Questions → MCQ Traps.
| Category | Topics |
|---|---|
| Foundations & Architectural Models | Fundamental Concepts, Overview of a Computer System, Evolution & Performance Languages, System Level Architecture, Virtual Machines, Harvard vs Von Neumann Architecture |
| Processor & CPU Design | Processor Types, Processor Types and Performance, CPU Architecture, Performance Metrics, CISC vs RISC |
| Instructions, Execution & Control | Machine Instructions, Instruction Execution Cycle, Control Unit and Instruction Processing |
| Data Representation & Arithmetic | Data Representation, Arithmetic Microprocessor |
| Parallel & Multi-Core Architecture | Parallel Computer Architecture (overview), ILP & Superscalar Processors, Parallel Processing, Multi-Processor and Multi-core Systems |
| Memory System | Memory Hierarchy, Cache Memory, Memory Organization, External Memory, RAID |
| I/O & System Interconnection | Computer Function and Interconnections, Input/Output System, I/O Types, BUS |
The conceptual groundwork — what a computer system is, how it's viewed at different abstraction levels, and the two classic organisational models everything else builds on.
Fundamental Concepts (Architecture)
Evolution & Performance Languages
Harvard and Non-Neumann Architecture (2017)
Processor classification, internal CPU structure, how performance is measured, and the CISC/RISC design philosophies.